Recently, a liquid crystal display device (LCD), featured by thin thickness, lightness of weight and low power consumption, has become popular as a display device, and is now in use for a display device of a mobile information terminal device, such as a portable telephone set (mobile phone or cellular phone), PDA (personal digital assistant) or a notebook PC.
However, the technique for enlarging the size of the liquid crystal display device or for coping with moving pictures has advanced such that not only the LCD for mobile use but also the stationary type large screen display device or a large screen liquid crystal television receiver has become a reality. As the liquid crystal display device, a liquid crystal device of an active matrix driving system, providing for high definition display, is currently in use.
Referring first to FIG. 29, a typical configuration of the liquid crystal display device of the active matrix driving system is explained. In FIG. 29, the major configuration of the connected to a pixel of a liquid crystal display unit is schematically shown by an equivalent circuit.
In general, a display unit 960 of a liquid crystal display device of the active matrix driving system is made up by a semiconductor substrate, including a matrix array of transparent pixel electrodes 964 and thin-film transistors (TFTs) 963, a counter-substrate having a transparent electrode 966 on the entire surface, and a liquid crystal sealed in-between the two substrates. The semiconductor substrate includes the matrix array of 1280×3 columns of pixels by 1024 rows of pixels in the case of a color SXGA panel, as an example.
The TFT 963, having the switching function, has its on/off controlled by the scanning signal, such that, when the TFT 963 is turned on, the grayscale voltage corresponding to a video signal is applied to the pixel electrode 964, and the liquid crystal has its transmittance changed by the potential difference across the pixel electrodes 964 and the electrode of the counter-substrate 966. This potential difference is maintained by a liquid crystal capacitance 965 for a preset time to display a picture.
On the semiconductor substrate, data lines 962 for sending a plurality of levels of voltage (grayscale voltages) applied to the respective pixel electrodes 964 and scanning lines 961 each for sending the scanning signal are arranged in a lattice form (in the case of the color SXGA panel, 1280×3 data lines and 1024 scanning lines are arranged). The scanning lines 961 and the data lines 962 become large capacitive loads due to capacitances generated at mutual intersections and liquid crystal capacitances sandwiched with the opposed substrate electrode.
The scanning signal is supplied to a scanning line 961 by a gate driver 970, and supply of the grayscale voltage to each of the pixel electrodes 964 is performed from a data driver 980 through a data line 962.
Rewriting of data for one screen is performed in one frame period ( 1/60 seconds), and each pixel row (each line) is selected one by one for each scanning line. The grayscale voltage is supplied from each data line within the period of the selection.
While the gate driver 970 should supply at least a binary scanning signal, the data driver 980 needs to drive the data lines by multi-levels of grayscale voltages corresponding to the number of grayscales. For this reason, as the buffer unit of the data driver 980, a differential amplifier that can perform voltage output with high precision is employed.
Further, in recent years, higher picture quality (creation of multiple colors) has been pursued, so that the demand for at least 260 thousand colors (6-bit video data for each of RGB), and further the demand for 26,800 thousand colors (8-bit video data for each of RGB) or more have increased.
For this reason, the data driver that outputs grayscale voltages corresponding to multi-bit video data is required to perform voltage output with an extremely high degree of precision. Further, the number of devices in a circuit unit for processing the video data has increased, and a chip area in a data driver LSI has increased, thereby becoming a factor causing higher cost. This problem will be described below in detail.
FIG. 30 is a diagram showing a configuration of the data driver 980 in FIG. 29, and shows the pertinent portion of the data driver 980 in the form of blocks. Referring to FIG. 30, the data driver 980 includes a latch address selector 981, a latch 982, a grayscale voltage generating circuit 983, a plurality of decoders 984, and a plurality of buffer circuits 985.
The latch address selector 981 determines a timing of a data latch based on a clock signal CLK. The latch 982 latches digital video data based on the timing determined by the latch address selector 981, and outputs latched data to each of the decoders 984 in unison according to an STB (strobe) signal. The grayscale voltage generating circuit 983 generates grayscale voltages with the number of grayscales corresponding to the video data. Each decoder 984 selects one of the grayscale voltages corresponding to the input data, for output. Each buffer circuit 985 inputs the grayscale voltage output from the decoder 984, and current amplifies the input grayscale voltage, for output as an output voltage Vout.
When 6-bit video data is input, for example, the number of grayscales is 64. Thus, the grayscale voltage generating circuit 983 generates grayscale voltages at 64 levels. Each decoder includes a circuit for selecting one of the grayscale voltages at 64 levels.
On the other hand, when 8-bit video data is input, the number of grayscales becomes 256. Thus, the grayscale voltage generating circuit 983 generates grayscale voltages at 256 levels. Each decoder includes a circuit for selecting one of the grayscale voltages at 256 levels.
When multiple bits are used in this manner, the circuit sizes of the grayscale voltage generating circuit 983 and the decoders 984 increase. When an increase from six bits to eight bits is made, the circuit sizes become four times or larger. Accordingly, the chip area of the LSI of the data driver increases to bring about a higher cost due to use of multiple bits.
On contrast therewith, configurations that restrict an increase in the chip area of the data driver LSI to a minimum even if multiple bits are used are proposed in patent documents 1 and 2, which will be hereinafter described. FIG. 31 shows an example of the configuration proposed in patent document 1 which will be hereinafter described (corresponding to FIG. 16 in patent document 1 that will be hereinafter described).
Referring to FIG. 31, this data driver is different from the data driver shown in FIG. 30 in the configurations of the grayscale voltage generating circuit 986, decoders 987, and buffer circuits 988. In the data driver in FIG. 31, the grayscale voltage generating circuit 986 generates a grayscale voltage each for two grayscales, and reduces the number of grayscale voltage lines for the decoders 987 to about a half of those for the decoders 984 in FIG. 31. Each decoder 987 selects two grayscale voltages according to video data, for output to a buffer circuit 988. The buffer circuit 988 can current amplifies input two grayscale voltages and a grayscale voltage intermediate between the two grayscale voltages, for output.
Proposals by the hereinafter-described patent documents 1 and 2 are to halve the number of grayscale voltage lines for each decoder 987, reduce the circuit size of the decoders 987, and aim at implementation of area saving or lower cost, by including the buffer circuits 988 inputting two grayscale voltages and outputting one of the two grayscale voltages and their intermediate voltage. Accordingly, even if multiple bits are used, an increase in the chip area of the data driver LSI can be more or less restricted.
As the differential amplifiers suitable for the buffer circuits 988, configurations shown in FIG. 5B in the hereinafter-described patent document 1 and shown in FIG. 15 in the hereinafter-described patent document 2 are proposed. In the configuration shown in FIG. 5B in the hereinafter-described patent document 1, the output of the differential pair becomes the input terminal of a diode-connected current mirror, so that it is considered that the configuration does not function as the differential amplifier. From FIG. 15 in the hereinafter-described patent document 2 pertinent to the hereinafter-described patent document 1, it is conjectured that the typical characteristic of the differential amplifiers proposed in the hereinafter-described patent documents 1 and 2 resides in a differential amplifier having a differential stage 910, as shown in FIG. 32, for example (based on the result of study by the inventor of the present invention).
FIG. 32 shows a configuration of the two-input differential amplifier. The differential stage 910 is characterized in that each of transistors 901 and 902 constituting a first differential pair is connected in parallel with transistors 903 and 904 constituting a second differential pair. Each of the differential pairs is driven by a common current source 907. Gray-scale voltages Vp1 and Vp2 are input to the gates of the transistors 901 and 903, respectively. The gates of the transistors 902 and 904 are connected in common to feedback an output Vn1 of the differential amplifier. The output pairs of the first and second differential pairs are connected to the input terminal and the output terminal of the current mirror (905, 906), respectively, and performs an amplification operation according to an output signal common to the first and second differential pairs.
In the differential amplifier having the above-mentioned configuration,                when the voltages Vp1 and Vp2 are the same input voltages, the output voltage Vn1 becomes equal to the input voltages, and        when the voltages Vp1 and Vp2 are different, the output voltage Vn1 becomes the voltage intermediate between the voltages Vp1 and Vp2.        
In the hereinafter-described patent document 3, a configuration including a string DAC (digital-to-analog converter) and an interpolation DAC is disclosed. The interpolation DAC includes a plurality of differential pairs. Ones of the input pairs of the differential pairs are connected to the output of the string DAC through respective switches. The others of the input pairs of the differential pairs are connected in common to an output terminal. Ones and the others of the output pairs of the differential pairs are connected in common to pairs of load devices and also connected to differential input pairs in an amplification stage. The output of the amplification stage is connected to an output terminal.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-34234A (FIG. 5, FIG. 20, FIG. 21).
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2001-343948A (FIG. 15).
[Patent Document 3]
U.S. Pat. No. 6,246,351 (FIG. 1).